Simple one-bus CPU architecture

To keep this as simple as reasonably possible, we consider a simple instruction format in which every instruction is entirely represented in one word. That is, the word is divided into fields such as "opcode", "register number", and "memory address", which are always the same for all instructions, quite unlike the PDP-11 case. Furthermore, the memory address appears directly in the instruction word, not in a subsequent word (perhaps the words are wider than 16 bits).

Here is a simple one-bus architecture we'll use for most of our examples in this course. Data paths represented by the large arrows (namely, each arrow to or from the bus except for the ALU input, plus Z_in) correspond to microprogram control lines.

Control lines also include Read and Write (memory functions), Wait MFC, the ALU functions, Set CC, Set Carry-In, Carry-Forward, Zero A, Complement B, and End.

Set CC causes the condition codes to be set by the current ALU operation. That is, it's the LOAD line for the condition code register.

Carry-Forward causes the C condition code to be supplied as Carry-In (i.e. the carry out from a previous ALU operation is supplied as the carry in to the new ALU operation). Set Carry-In supplies an unconditional '1' as Carry-In.

"Zero A" provides a zero value to the ALU which can be used in the same cycle, without affecting the contents of Y. That is, Zero A overrides the Y output with a zero value.

"Complement B" flips all of the bits in the 'B' ALU input (the one from the bus). This helps with two's-complement subtraction (which usually then also uses Set Carry-In to add one).

End makes the current microinstruction the last microinstruction of the microroutine by resetting the µPC.

There are also eight conditional microbranch control lines, of the form "If C then End", "If then End", and so on for all of C, V, Z, and N. ALU operations only set the condition codes if the Set CC bit is on (else we couldn't implement branch instructions with an offset without ruining the condition codes!). Note that when a microbranch is taken, the current microinstruction still completes, just as it does with the End control line.

This is part of the "microprogramming notes" web pages, which contain the following subtopics:

1. Simple one-bus CPU architecture    <-- you are here
2. Register in / out connections
3. Microcode examples
4. ALU architecture (insides)
5. ALU interface (outsides)
6. Control circuitry
7. Simple two-bus CPU architecture
8. Simple three-bus CPU architecture (used in RISCs)