Control circuitry for the simple CPU microarchitecture

The µPC is controlled by the clock; LOAD and INCR don't perform these operations immediately, they just control whether these operations will be performed at the next clock cycle.

The µPC is a combination of a register and a counter, just as the "shift register with parallel load" is a combination of a shift register and a normal register. As such, it's not actually much tricker than the two separately; just much messier inside.

"End" is the same as "Go To" and "µbranch-target = 0".

(WaitMFC and not(MFC)) makes the µPC stay as is, so the input to the control store stays as is, so the output of the control store stays as is, so WaitMFC stays on, so this continues until not(MFC) becomes false, i.e. MFC becomes true. This is how WaitMFC works.

You don't have to be able to reproduce the above diagram, or anything like it, for the final exam. It's here to clarify matters which are more centrally a part of the course, and also to demonstrate that we really have shown how to implement a CPU with gates and such.

This is part of the "microprogramming notes" web pages, which contain the following subtopics:

1. Simple one-bus CPU architecture
2. Register in / out connections
3. Microcode examples
4. ALU architecture (insides)
5. ALU interface (outsides)
6. Control circuitry    <-- you are here
7. Simple two-bus CPU architecture
8. Simple three-bus CPU architecture (used in RISCs)