Of course I could ask you simply to write some code, like the programming problems we've been doing in VELMA, as done in the last tutorial.
Here are some further possible kinds of problems.
1. The "delayed branch rule" on some RISC CPUs says that the instruction following a branch is executed even if the branch is taken. That is, in the instruction sequence
100 | ADD R0, R1, R2 |
101 | JUMP 110 |
102 | ADD R3, R4, R5 |
To write programs for this situation we sometimes first write out the programs with NOP instructions (does nothing) in the delayed branch slot, then rearrange the steps to try to avoid wasting a cycle on the execution of the NOP.
For each of the following instruction sequences, either rearrange it to speed it up, or explain why it cannot be improved.
(a)
ADD R0, R1, R2 ADD R3, R3, R3 BEQ 110 NOP
(b)
ADD R0, R1, R2 JUMP 110 NOP
(c)
ADD R0, R1, R2 BEQ 110 NOP
2. The "delayed load rule" on some RISC CPUs says that the instruction immediately following a LOAD may not reference the target register of the LOAD operation (either as operand source or result destination). That is, in the instruction sequence
100 | LOAD 500, R3 |
101 | ADD R0, R1, R2 |
102 | ADD R3, R4, R5 |
(a)
LOAD 500, R3 ADD R3, R3, R3 LOAD 502, R2 ADD R2, R2, R2(b)
LOAD 500, R1 LOAD 502, R2 ADD R1, R2, R3(c)
ADD R0, R1, R2 LOAD 500, R3 ADD R0, R2, R3Answers to both the above questions