In this file I'll go through answering the same question for a standard SR latch (the one with two NOR gates, and the wires crossing over, and no other gates). (Obviously, the answer as to whether or not it's useful is going to be "yes".)
For the purposes of this investigation, let's name the top output (the one connected to the 'R' NOR gate) "Qa" and the bottom one "Qb", as in the figure on the top of page 691 of HVZ 5e, rather than the "Q" and "Q bar" I used in lecture. This is because we don't know in advance that the bottom output is always the negation of the top output; in fact, this is not always the case when the latch is not used "properly" (e.g. if S=R=1 sometimes). And if we're just starting to investigate its behaviour, we don't yet know how to use it properly or effectively.
(Note that I've put 'R' on top there and 'S' on bottom, so that on the output side we can have 'Q' on top and 'Q bar' on bottom. And to remember that Qb is the Qbar below, well, you could pretend that 'b' stands for 'bar'.)
For inputs S=R=0, let us consider all four possible outputs and see whether they are stable states.
If Qa=Qb=0, then the NOR gates' inputs are all 0, thus their outputs will be 1 (thus changing Qa and Qb). Thus Qa=Qb=0 is not a stable state. Saying that it is "not a stable state" means simply that it won't stay in that state; we have determined that it will change to something else. It doesn't really matter what else right now, as we'll be looking at that other state in its turn. (It also doesn't matter if it ends up coming back to Qa=Qb=0 later, because we've just established that it's not going to stay there.)
Now, the next possible output pair. If Qa=0 and Qb=1, then if you look at the inputs to the NOR gates and their supposed output, you will see that you have a match. This is a stable state because it is possible for it to stay that way. Similarly, Qa=1 and Qb=0 is a stable state (for inputs S=R=0).
If Qa=Qb=1, then the inputs to the NOR gates are each 0 and 1, and so their outputs will be 0, so this is not a stable state.
In summary,
Now let us consider other inputs. Suppose that S=1 and R=0. We can see that the Qb NOR gate will necessarily output 0, since an input of 1 is a base law for OR; that is, the OR is 1, so the NOR is 0. Thus any stable state will have Qb=0.
Since any stable state will have Qb=0, we know what the inputs to the Qa NOR gate will be: R=0 and Qb=0. So that NOR gate will output 1, i.e. Qa=1.
Thus the only possible stable state is Qa=1 and Qb=0. But don't write that down yet! This does not establish that Qa=1 and Qb=0 is a stable state; we've merely shown that all other output states are not stable.
But in fact if you look at the inputs to each of the NOR gates for S=1 and R=0 and Qa=1 and Qb=0, you will see that this is indeed a stable state. The Qa NOR gate has inputs 0 (R) and 0 (Qb), so it will output 1, which is what is already there; and the Qb NOR gate has inputs 1 (S) and 1 (Qa), so it will output 0, which is what is already there. It won't change; it's stable.
The case S=0 and R=1 is just the vertically-flipped mirror image of the case S=1 and R=0, so from the above , we know that the only stable output state is Qa=1 and Qb=0.
This leaves the case S=R=1. In this case we see that the NORs will both output 0, by the above-mentioned base law. Furthermore, if you trace those outputs around back to the NOR inputs, you'll see that the NOR gates each have one input of 1 and one input of 0, and 1 NOR 0 = 0, so this is a stable state, and the only one.
So, can we use this as a one-bit memory? Yes, if we avoid the input state S=R=1. If S and R are usually zero, then if you raise one of them to 1 and then return it to 0 after the circuit stabilizes, then when S=R=0 again you will see the outputs 1,0 iff it was S you raised to 1 and the outputs 0,1 iff it was R you raised to 1, and both of these output states are stable for S=R=0.